The present invention relates to non-volatile memory transistors. More specifically, the present invention relates to a method and structure of using a 2-bit non-volatile memory transistor to form a flash memory transistor array.
A 2-bit non-volatile semiconductor memory transistor has been described in U.S. Pat. No. 5,768,192, to Eitan. However, the manners of using 2-bit NVM transistors in a memory array have not yet been fully developed.
One memory array that implements 2-bit NVM transistors is described in U.S. Pat. No. 6,181,597 to Nachumovsky.
FIG. 1 is a schematic diagram illustrating a conventional memory block 100. Memory block 100 implements uses a plurality of 2-bit memory transistors, which are identified as memory transistors MX,Y, where X and Y represent the row and column locations, respectively, of the memory transistors within memory block 100. Thus, memory block 100 includes memory transistors M0,0-M3,6. The rows extend along a first axis, and the columns extend along a second axis, perpendicular to the first axis.
Each of the memory transistors M0,0-M3,6 includes two charge trapping regions, namely, a left charge trapping region and a right charge trapping region, thereby enabling each of memory transistors M0,0-M3,6 to store 2-bits of data.
The source and drain regions of memory transistors M0,0-M3,6 are formed by diffused regions 101-108, which extend in parallel along the second axis. Diffused regions 101-108 also operate as bit lines within memory block 100. Thus, diffused regions 101-108 are referred to as diffusion bit lines.
ONO structures 111-117 are located between adjacent diffusion bit lines 101-108, as illustrated. The gates of the memory transistors in each row are commonly connected to a word line. More specifically, the memory transistors of rows 0-3 are connected to word lines WL0-WL3, respectively.
The 2-bit memory transistors of memory block 100 are accessed through high-voltage select transistors 131-138 and metal bit lines 141-144. Metal bit lines 141-144 are located in an interconnect layer that extends over the above-described elements of memory block 100. High-voltage select transistors 131-138 are designed to have gate oxide sufficient to withstand the high voltages required for programming and erasing the memory transistors. In general, select transistors 131-138 are controlled to selectively connect metal bit lines 141-144 to diffusion bit lines 101-108.
FIG. 2 is a cross sectional view of memory transistors M0,0 and M0,1 along the first axis through word line WL0. Diffusion bit lines 101-103 are n-type regions formed in a p-type silicon semiconductor region 110. Bit line oxide regions 124 are formed over the diffusion bit lines 101-103. Because the memory transistors in memory block 100 do not require field oxide for isolation, memory block 100 can be referred to as a fieldless array. ONO structures 111 and 112 extend over bit line insulating regions 124, diffusion bit lines 101-103 and substrate 110 in the manner illustrated. Word line WL0 is a polycide or salicide structure that includes a layer of conductively doped polycrystalline silicon 126 and an overlying layer of metal silicide 127, and extends over ONO structures 111 and 112 (and bit line insulating regions 124). Word lines WL0 forms the control gate of memory transistors M0,0 and M0,1. The fabrication of memory block 100 is described in U.S. Pat. No. 6,346,442 by Aloni et al.
Typical problems associated with memory block 100 and the corresponding memory transistors include (1) relatively large source/drain series resistances due to the use of diffusion bit lines, (2) relatively deep source/drain junction depths due to the high thermal budget required by bit line oxidate regions, (3) an unadaptable structure with respect to advanced CMOS technology using self-aligned salicidation process (i.e., almost impossible to implement self-aligned salicide on word lines and source/drain regions), and (4) high bit line-to-bit line leakage, because the memory transistors are separated by active regions, without any general isolation structure.
It would therefore be desirable to have a flash memory array structure that implements 2-bit non-volatile memory transistors and exhibits a relatively low source/drain series resistance, and a relatively low bit line resistance. It would further be desirable if the source/drain junction depth of the memory transistors in the array are relatively shallow (e.g., less than 0.1 microns). It would further be desirable if the flash memory array structure were capable of implementing a self-aligned salicidation process over both the gate and source/drain regions of the array. It would also be desirable if there were no leakage issues between bit lines of the flash memory array. It would further be desirable if the flash memory array exhibits low word line capacitance, thereby resulting in low RC delay and high-speed operation.
Accordingly, the present invention provides an improved array structure for implementing a flash memory array using 2-bit non-volatile memory transistors. For purposes of this disclosure, a flash memory array is defined as a non-volatile memory array that cannot be erased on a word-by-word basis, but which must be erased in blocks. The present invention also provides a method for fabricating this improved array structure, which is largely compatible with a conventional CMOS process flow.
In accordance with one embodiment, a non-volatile memory (NVM) array is fabricated with a plurality of 2-bit NVM transistors arranged in a plurality of rows extending along a first axis, and a plurality of columns extending along a second axis, perpendicular to the first axis. The non-volatile memory array includes a plurality of field isolation regions located in a semiconductor substrate. In a preferred embodiment, the field isolation regions are shallow trench isolation (STI) regions.
A plurality of word lines extend over the semiconductor substrate along the first axis, wherein the word lines also form control gates of the 2-bit NVM transistors. Oxide-nitride-oxide (ONO) structures are located between the substrate and the word lines, wherein the nitride layer of the ONO structures provides floating gate storage for the NVM transistors. A plurality of H-shaped source/drain regions are defined by the field isolation regions and the word lines, wherein each source/drain region serves as a source/drain for four different NVM transistors in the array. Self-aligned silicide can be formed over both the word lines and the source/drain regions.
Because each source/drain region only serves as a source/drain region for four different NVM transistors (and not an entire diffusion bit line), the array structure of the present invention advantageously provides a low source/drain series resistance and relatively low bit line resistances.
The present invention also includes a method of fabricating an array of 2-bit NVM cells, wherein the method includes (1) forming a plurality of field isolation regions in a semiconductor substrate, (2) forming a lower dielectric layer over the semiconductor substrate, (3) forming a floating gate dielectric layer over the lower dielectric layer, (4) forming an upper dielectric layer over the floating gate dielectric layer, (5) forming a gate electrode layer over the upper dielectric layer, (6) patterning the gate electrode layer, the upper dielectric layer and the floating gate dielectric layer, wherein the gate electrode layer is patterned to form a plurality of word line/control gate structures extending along a first axis, and wherein the floating gate dielectric layer is patterned to form a plurality of floating gate structures, and (7) forming H-shaped source/drain regions having a first conductivity type in the substrate, the H-shaped source/drain regions being defined by the word line/control gate structures and field isolation regions.
In one embodiment, the lower dielectric layer is formed by thermally oxidizing the upper surface of the substrate. The floating gate dielectric layer can be formed by depositing a silicon nitride layer over the lower dielectric layer. The upper dielectric layer can be formed by thermally oxidizing the upper surface of the floating gate dielectric layer and/or depositing a silicon oxide layer over the floating gate dielectric layer.
The gate electrode layer can be formed by depositing a polysilicon layer over the upper dielectric layer. The polysilicon layer can be doped to the first conductivity type or a second conductivity type, opposite the first conductivity type. A refractory metal layer or a metal silicide layer can be deposited over the polysilicon layer, thereby forming a polycide gate electrode. In another embodiment, self-aligned salicide regions are formed over both the word line/control gate structures and the source/drain regions.
The source/drain regions are fabricated in accordance with conventional processing techniques, and are not required to extend under bit line oxidation in the manner illustrated in FIG. 2 above. As a result, the source/drain junction depth of the NVM transistors in the array are advantageously relatively shallow.